1. Field of the Invention
This invention relates generally to the area of conservation of power in a receiver synchronously detecting at least one predetermined signal within an information signal, and more particularly to a method and apparatus for conserving power for a portion of the reception of the information signal while attempting to detect the at least one predetermined signal.
2. Description of the Prior Art
Synchronous detection of information signals is provided for in a digital signaling protocol proposed by British Telecom in England which is commonly termed POCSAG (Post Office Code Standardization Advisory Group). FIG. 1 shows a typical POCSAG protocol signal 10, and a power conservation strobe 20, used in prior art receivers. The synchronization signal corresponds to the sync code 12a and 12b. The sync code is a predefined 32 symbol word occurring at the beginning of a batch. The POCSAG protocol is transmitted on a radio frequency carrier and is modulated using binary FSK, consequently one symbol corresponds to one binary bit in the POCSAG protocol. Each batch has a sync code 12 and eight frames of information 21-28. Each frame has two information words corresponding to information signals. An information word is a 32 bit binary word having 21 information bits and 11 parity bits. The information word is structured as a 31,21 extended BCH word having one extra parity bit, henceforth referred to as a 32,21 BCH word.
Area 30 of FIG. 1 represents a time when no signal is transmitted. The POCSAG signal begins with a preamble 32. The first batch begins with a first sync code 12a. During the time spanning intervals 30, 32 and 12a, the receiver performs a sync acquisition process as indicated by area 52 of line 20 using processes well known in the art. After acquiring sync, the receiver begins a batch decoding process wherein the receiver decodes information within a preassigned frame. The information words within the frame may include an address matching a predetermined address assigned to the receiver, in response to which the receiver would alert. The information words within the frame may include addresses for other pagers, or message data associated with an address, or idle code words.
Assume the receiver operating per FIG. 1 has been preassigned to frame 4. Having acquired sync at the end of interval 52, the receiver conserves power during interval 53a. The receiver operates in a high power mode during interval 54a in order to decode information within frame 4. During interval 55a, the receiver operates in a low power mode until interval 56b wherein the receiver operates in a high power mode in order to receive the second sync code 12b. The power conservation cycle repeats for intervals 53b, 54b and 55b.
Events during intervals 54a and 54b are shown in greater detail. A representative frame from line 10 shown as line 10a has two 32 bit information words, WORD 1, 60, and WORD 2, 62. The contents of the first information word, 60 is 1 0011 0011 0001 0001 0110 0100 0011 101. The leading bit being a "1" indicates the information word is a data word. The contents of the second information word, 62, is 0 1101 0010 1100 1010 1100 0000 0011 011. The leading bit being a "0" indicates the information word is an address word. Line 64 shows an example of a predetermined address of the receiver. The address is 0 0101 0011 1000 1010 1100 1011 1111 000.
In this example the receiver has a single address. The address of the receiver is shown under WORD 1, 60, and repeated under WORD 2, 62, so that a visual comparison may be made between the information words and the receiver address. Note that neither information word substantially matches the receiver address. Between each information word and the receiver address is a line of "*" symbols, 66, representing bits where the content of the information word differs from the content of the receiver address. Note that in the first word, differences occur in bit locations 1, 3, 4, 10, 13, 14, 16-18, 20, 22-27, 30 and 32. In the second word, bit differences occur in bit locations 2, 9, 1, 22, 24-27, 31 and 32. Line 20a shows in greater detail the operation of the power strobe during the two information words. Note that the power strobe is active for the entire portion of each information word. The 32,21 code allows for two bits of correction while searching for an address, it follows that if a bit difference of three or grater is found, the address will not be detected. In the information words of FIG. 1, the three bit difference is found after the 4th bit of the WORD 1 and after the 11th bit of the WORD 2. However, prior art receivers remain active for the entire 32 bit information word.
With the growing success of digital paging systems, and the ever decreasing size of paging receivers and batteries, and consequently battery capacity, it is desirable to conserve power whenever possible. Advances in receiver technology have provided means for rapidly switching receivers ON which makes additional power conservation techniques a possibility. Additional power conservation may be realized by conserving power during a portion of an information word.